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preliminary publication# 21557 rev: c amendment/ 0 issue date: april 1998 am29lv001b 1 megabit (128 k x 8-bit) cmos 3.0 volt-only boot sector flash memory distinctive characteristics n single power supply operation full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors n manufactured on 0.35 m process technology n high performance full voltage range: access times as fast as 55 ns regulated voltage range: access times as fast as 45 ns n ultra low power consumption (typical values at 5 mhz) 200 na automatic sleep mode current 200 na standby mode current 7 ma read current 15 ma program/erase current n flexible sector architecture one 8 kbyte, two 4 kbyte, and seven 16 kbyte supports full chip erase sector protection features: hardware method of locking a sector to prevent any program or erase operations within that sector sectors can be locked in-system or via programming equipment temporary sector unprotect feature allows code changes in previously locked sectors n unlock bypass mode program command reduces overall programming time when issuing multiple program command sequences n top or bottom boot block configurations available n embedded algorithms embedded erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors embedded program algorithm automatically writes and verifies data at specified addresses n minimum 1,000,000 write cycle guarantee per sector n package option 32-pin tsop 32-pin plcc n compatibility with jedec standards pinout and software compatible with single- power supply flash superior inadvertent write protection n data# polling and toggle bits provides a software method of detecting program or erase operation completion n erase suspend/erase resume supports reading data from or programming data to a sector that is not being erased n hardware reset pin (reset#) hardware method for resetting the device to reading array data
am29lv001b 2 preliminary general description the am29lv001b is a 1 mbit, 3.0 volt-only flash memory device organized as 131,072 bytes. the am29lv001b has a boot sector architecture. the device is offered in 32-pin plcc and 32-pin tsop packages. the byte-wide (x8) data appears on dq7C dq0. all read, erase, and program operations are accomplished using only a single power supply. the device can also be programmed in standard eprom programmers. the standard am29lv001b offers access times of 45, 55, 70, and 90 ns, allowing high speed microproces- sors to operate without wait states. to eliminate bus contention, the device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. the device requires only a single power supply (2.7 vC3.6v) for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. the am29lv001b is entirely command set compatible with the jedec single-power-supply flash standard . commands are written to the command reg- ister using standard microprocessor write timings. reg- ister contents serve as input to an internal state- machine that controls the erase and programming cir- cuitry. write cycles also internally latch addresses and data needed for the programming and erase opera- tions. reading data out of the device is similar to reading from other flash or eprom devices. device programming occurs by executing the program command sequence. this initiates the embedded program algorithman internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. the unlock bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four. device erasure occurs by executing the erase com- mand sequence. this initiates the embedded erase algorithman internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. during erase, the device automatically times the erase pulse widths and verifies proper cell margin. the host system can detect whether a program or erase operation is complete by reading the dq7 (data# polling) and dq6 (toggle) status bits . after a program or erase cycle has been completed, the device is ready to read array data or accept another command. the sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. hardware data protection measures include a low v cc detector that automatically inhibits write opera- tions during power transitions. the hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. this can be achieved in-system or via program- ming equipment. the erase suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. true background erase can thus be achieved. the hardware reset# pin terminates any operation in progress and resets the internal state machine to reading array data. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the flash memory. the device offers two power-saving features. when ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . the system can also place the device into the standby mode . power consumption is greatly reduced in both these modes. amds flash technology combines years of flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. the device electrically erases all bits within a sector simultaneously via fowler-nordheim tun- neling. the data is programmed using hot electron injection.
3 am29lv001b preliminary product selector guide note: see ac characteristics for full specifications. block diagram family part number am29lv001b speed options regulated voltage range: v cc =3.0C3.6 v -45r full voltage range: v cc = 2.7C3.6 v -55 -70 -90 max access time, ns (t acc ) 45 55 70 90 max ce# access time, ns (t ce ) 45 55 70 90 max oe# access time, ns (t oe ) 25 30 30 35 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# ce# oe# stb stb dq0 C dq7 sector switches reset# data latch y-gating cell matrix address latch a0Ca16 21557c-1
am29lv001b 4 preliminary connection diagrams 1 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 32 17 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a11 a9 a8 a13 a14 nc we# v cc reset# a16 a15 a12 a7 a6 a5 a4 oe# a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 a3 1 16 2 3 4 5 6 7 8 9 10 11 12 13 14 15 a11 a4 a9 a8 a13 a14 nc we# v cc reset# a16 a15 a12 a7 a6 a5 32 17 31 30 29 28 27 26 25 24 23 22 21 20 19 18 oe# a3 a10 ce# dq7 dq6 dq5 dq4 dq3 v ss dq2 dq1 dq0 a0 a1 a2 21557c-2 32-pin reverse tsop 32-pin standard tsop dq6 reset# dq5 dq4 dq3 13130 2 3 4 5 6 7 8 9 10 11 12 13 17 18 19 20 16 15 14 29 28 27 26 25 24 23 22 21 32 a7 a6 a5 a4 a3 a2 a1 a0 dq0 a14 a13 a8 a9 a11 oe# a10 ce# dq7 a12 a15 a16 v cc we# nc dq1 dq2 v ss am29lv001 plcc
5 am29lv001b preliminary pin configuration a0Ca16 = 17 addresses dq0Cdq7 = 8 data inputs/outputs ce# = chip enable oe# = output enable we# = write enable reset# = hardware reset pin, active low v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v ss = device ground nc = pin not connected internally logic symbol 21557c-3 17 8 dq0Cdq7 a0Ca16 ce# oe# we# reset#
am29lv001b 6 preliminary ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combi- nation) is formed by a combination of the elements below. valid combinations valid combinations list configurations planned to be sup- ported in volume for this device. consult the local amd sales office to confirm availability of specific valid combinations and to check on newly released combinations. device number/description am29lv001b 1 megabit (128 k x 8-bit) cmos flash memory 3.0 volt-only read, program, and erase c e -45r am29lv001b t optional processing blank = standard processing b = burn-in (contact an amd representative for more information) temperature range c= commercial (0c to +70c) i = industrial (C40c to +85c) e = extended (C55c to +125c) package type e = 32-pin thin small outline package (tsop) standard pinout (ts 032) f = 32-pin thin small outline package (tsop) reverse pinout (tsr032) j = 32-pin rectangular plastic leaded chip carrier (pl 032) speed option see product selector guide and valid combinations boot code sector architecture t = top sector b = bottom sector valid combinations am29lv001bt-45r, am29lv001bb-45r, ec, fc, jc am29lv001bt-55, am29lv001bb-55, ec, ei, ee, fc, fi, fe, jc, ji, je am29lv001bt-70, am29lv001bb-70, am29lv001bt-90, am29lv001bb-90,
7 am29lv001b preliminary device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register it- self does not occupy any addressable memory loca- tion. the register is composed of latches that store the commands, along with the address and data informa- tion needed to execute the command. the contents of the register serve as inputs to the internal state ma- chine. the state machine outputs dictate the function of the device. table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the following subsections describe each of these operations in further detail. table 1. am29lv001b device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 12.0 0.5 v, x = dont care, a in = address in, d in = data in, d out = data out notes: 1. addresses are a16Ca0. 2. the in-system method of sector protection/unprotection is available. sector protection/unprotection can be implemented by using programming equipment. see the sector protection/unprotection section. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output con- trol and gates array data to the output pins. we# should remain at v ih . the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory con- tent occurs during the power transition. no command is necessary in this mode to obtain array data. stand- ard microprocessor read cycles that assert valid ad- dresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see reading array data for more information. refer to the ac read operations table for timing specifica- tions and to figure 13 for the timing diagram. i cc1 in the dc characteristics table represents the active cur- rent specification for reading array data. writing commands/command sequences to write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . the device features an unlock bypass mode to facili- tate faster programming. once the device enters the unlock bypass mode, only two write cycles are re- quired to program a byte, instead of four. the byte program command sequence section has details on programming data to the device using both standard and unlock bypass command sequences. an erase operation can erase one sector, multiple sec- tors, or the entire device. table 2 indicate the address space that each sector occupies. a sector address consists of the address bits required to uniquely select a sector. the command definitions section has de- tails on erasing a sector or the entire chip, or suspend- ing/resuming the erase operation. after the system writes the autoselect command se- quence, the device enters the autoselect mode. the system can then read autoselect codes from the inter- operation ce# oe# we# reset# addresses (note 1) dq0Cdq7 read l l h h a in d out write l h l h a in d in standby v cc 0.3 v x x v cc 0.3 v x high-z output disable l h h h x high-z reset x x x l x high-z sector protect (note 2) l h l v id sector address, a6 = l, a1 = h, a0 = l d in , d out sector unprotect (note 2) l h l v id sector address, a6 = h, a1 = h, a0 = l d in , d out temporary sector unprotect x x x v id a in d in
am29lv001b 8 preliminary nal register (which is separate from the memory array) on dq7Cdq0. standard read cycle timings apply in this mode. refer to the autoselect mode and autoselect command sequence sections for more information. i cc2 in the dc characteristics table represents the ac- tive current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. program and erase operation status during an erase or program operation, the system may check the status of the operation by reading the status bits on dq7Cdq0. standard read cycle timings and i cc read specifications apply. refer to write operation status for more information, and to ac characteris- tics for timing diagrams. standby mode when the system is not reading or writing to the de- vice, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. the device also enters the standby mode when the re- set# pin is driven low. refer to the next section, re- set#: hardware reset pin. if the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. i cc3 in the dc characteristics table represents the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the device automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# control signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. i cc5 in the dc characteristics table represents the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of reset- ting the device to reading array data. when the re- set# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state ma- chine to reading array data. the operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of the reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc4 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset cir- cuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firmware from the flash memory.the system may use the reset# pin to force the device into the standby mode. refer to the standby mode section for more in- formation. refer to the ac characteristics tables for reset# pa- rameters and to figure 14 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high imped- ance state.
9 am29lv001b preliminary table 2. am29lv001b top boot sector architecture table 3. am29lv001b bottom boot sector architecture sector a16 a15 a14 a13 a12 sector size (kbytes) address range (in hexadecimal) sa0 0 0 0 x x 16 kbytes 00000hC03fffh sa1 0 0 1 x x 16 kbytes 04000hC07fffh sa2 0 1 0 x x 16 kbytes 08000hC0bfffh sa3 0 1 1 x x 16 kbytes 0c000hC0ffffh sa4 1 0 0 x x 16 kbytes 10000hC13fffh sa5 1 0 1 x x 16 kbytes 14000hC17fffh sa6 1 1 0 x x 16 kbytes 18000hC1bfffh sa7 1 1 1 0 0 4 kbytes 1c000hC1cfffh sa8 1 1 1 0 1 4 kbytes 1d000hC1dfffh sa9 1 1 1 1 x 8 kbytes 1e000hC1ffffh sector a16 a15 a14 a13 a12 sector size (kbytes) address range (in hexadecimal) sa0 0 0 0 0 x 8 kbytes 00000hC01fffh sa1 0 0 0 1 0 4 kbytes 02000hC02fffh sa2 0 0 0 1 1 4 kbytes 03000hC03fffh sa3 0 0 1 x x 16 kbytes 04000hC07fffh sa4 0 1 0 x x 16 kbytes 08000hC0bfffh sa5 0 1 1 x x 16 kbytes 0c000hC0ffffh sa6 1 0 0 x x 16 kbytes 10000hC13fffh sa7 1 0 1 x x 16 kbytes 14000hC17fffh sa8 1 1 0 x x 16 kbytes 18000hC1bfffh sa9 1 1 1 x x 16 kbytes 1c000hC1ffffh
am29lv001b 10 preliminary autoselect mode the autoselect mode provides manufacturer and de- vice identification, and sector protection verification, through identifier codes output on dq7Cdq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. however, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires v id (11.5 v to 12.5 v) on address pin a9. address pins a6, a1, and a0 must be as shown in table 4. in addition, when verifying sector protection, the sector address must appear on the appropriate highest order address bits (see table 2). table 4 shows the remaining address bits that are dont care. when all necessary bits have been set as required, the program- ming equipment may then read the corresponding identifier code on dq7-dq0. to access the autoselect codes in-system, the host system can issue the autoselect command via the command register, as shown in table 5. this method does not require v id . see command definitions for details on using the autoselect mode. table 4. am29lv001b autoselect codes l = logic low = v il , h = logic high = v ih , sa = sector address, x = dont care. sector protection/unprotection the hardware sector protection feature disables both program and erase operations in any sector. the hard- ware sector unprotection feature re-enables both pro- gram and erase operations in previously protected sectors. sector protection/unprotection can be imple- mented via two methods. the primary method requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 1 shows the algo- rithms and figure 21 shows the timing diagram. this method uses standard microprocessor bus cycle tim- ing. for sector unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. the alternate method intended only for programming equipment requires v id on address pin a9, oe#, and reset#. this method is compatible with programmer routines written for earlier 3.0 volt-only amd flash de- vices. publication number 22134 contains further de- tails; contact an amd representative to request a copy. the device is shipped with all sectors unprotected. amd offers the option of programming and protecting sectors at its factory prior to shipping the device through amds expressflash? service. contact an amd representative for details. it is possible to determine whether a sector is protected or unprotected. see autoselect mode for details. temporary sector unprotect this feature allows temporary unprotection of previ- ously protected sectors to change data in-system. the sector unprotect mode is activated by setting the re- set# pin to v id . during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once v id is removed from the re- set# pin, all the previously protected sectors are protected again. figure 2 shows the algorithm, and figure 20 shows the timing diagrams, for this feature. description ce# oe# we# a16 to a12 a11 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 dq7 to dq0 manufacturer id : amd l l h x x v id xlxll 01h device id: am29lv001bt (top boot block) llhxxv id xlxlh edh device id: am29lv001bb (bottom boot block) llhxxv id xlxlh 6dh sector protection verification l l h sa x v id xlxhl 01h (protected) 00h (unprotected)
11 am29lv001b preliminary figure 1. in-system sector protect/unprotect algorithms sector protect: write 60h to sector address with a6 = 0, a1 = 1, a0 = 0 set up sector address wait 150 s verify sector protect: write 40h to sector address with a6 = 0, a1 = 1, a0 = 0 read from sector address with a6 = 0, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 m s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector unprotect mode no sector unprotect: write 60h to sector address with a6 = 1, a1 = 1, a0 = 0 set up first sector address wait 15 ms verify sector unprotect: write 40h to sector address with a6 = 1, a1 = 1, a0 = 0 read from sector address with a6 = 1, a1 = 1, a0 = 0 start plscnt = 1 reset# = v id wait 1 m s data = 00h? last sector verified? remove v id from reset# write reset command sector unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector unprotect mode no all sectors protected? yes protect all sectors: the indicated portion of the sector protect algorithm must be performed for all unprotected sectors prior to issuing the first sector unprotect address set up next sector address no yes no yes no no yes no sector protect algorithm sector unprotect algorithm first write cycle = 60h? protect another sector? reset plscnt = 1 21557c-4
am29lv001b 12 preliminary figure 2. temporary sector unprotect operation hardware data protection the command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to table 5 for com- mand definitions). in addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not ac- cept any write cycles. this protects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent uninten- tional writes when v cc is greater than v lko . write pulse glitch protection noise pulses of less than 5 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to reading array data on power-up. command definitions writing specific address and data commands or se- quences into the command register initiates device op- erations. table 5 defines the valid register command sequences. writing incorrect address and data val- ues or writing them in the improper sequence resets the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the appropriate timing diagrams in the ac characteristics section. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an embedded program or em- bedded erase algorithm. after the device accepts an erase suspend com- mand, the device enters the erase suspend mode. the system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. after completing a programming opera- tion in the erase suspend mode, the system may once again read array data with the same exception. see erase suspend/erase resume commands for more information on this mode. the system must issue the reset command to re-ena- ble the device for reading array data if dq5 goes high, or while in the autoselect mode. see the reset com- mand section, next. see also requirements for reading array data in the device bus operations section for more information. the read operations table provides the read parame- ters, and figure 13 shows the timing diagram. start perform erase or program operations reset# = v ih temporary sector unprotect completed (note 2) reset# = v id (note 1) notes: 1. all protected sectors unprotected. 2. all previously protected sectors are protected once again. 21557c-5
13 am29lv001b preliminary reset command writing the reset command to the device resets the de- vice to reading array data. address bits are dont care for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence be- fore programming begins. this resets the device to reading array data (also applies to programming in erase suspend mode). once programming begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during erase suspend). if dq5 goes high during a program or erase operation, writing the reset command returns the device to read- ing array data (also applies during erase suspend). see ac characteristics for parameters, and to figure 14 for the timing diagram. autoselect command sequence the autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. table 5 shows the address and data requirements. this method is an alternative to that shown in table 4, which is intended for prom programmers and requires v id on address bit a9. the autoselect command sequence is initiated by writ- ing two unlock cycles, followed by the autoselect com- mand. the device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. a read cycle at address xx00h retrieves the manufac- turer code. a read cycle at address xx01h returns the device code. a read cycle containing a sector address (sa) and the address 02h returns 01h if that sector is protected, or 00h if it is unprotected. refer to table 2 for valid sector addresses. the system must write the reset command to exit the autoselect mode and return to reading array data. byte program command sequence the device programs one byte of data for each program operation. the command sequence requires four bus cycles, and is initiated by writing two unlock write cy- cles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or tim- ings. the device automatically provides internally gen- erated program pulses and verify the programmed cell margin. table 5 shows the address and data require- ments for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and ad- dresses are no longer latched. the system can deter- mine the status of the program operation by using dq7 or dq6. see write operation status for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the program- ming operation. the byte program command se- quence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence and across sector boundaries. a bit cannot be programmed from a 0 back to a 1. attempting to do so may halt the operation and set dq5 to 1, or cause the data# polling algorithm to indicate the operation was suc- cessful. however, a succeeding read will show that the data is still 0. only erase operations can convert a 0 to a 1. unlock bypass command sequence the unlock bypass feature allows the system to pro- gram bytes to the device faster than using the standard program command sequence. the unlock bypass com- mand sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the unlock bypass command, 20h. the device then en- ters the unlock bypass mode. a two-cycle unlock by- pass program command sequence is all that is required to program in this mode. the first cycle in this se- quence contains the unlock bypass program com- mand, a0h; the second cycle contains the program address and data. additional data is programmed in the same manner. this mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. table 5 shows the requirements for the com- mand sequence. during the unlock bypass mode, only the unlock by- pass program and unlock bypass reset commands are valid. to exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. the first cycle must contain the data 90h; the second cycle the data 00h. addresses are dont cares for both cycles. the device then returns to reading array data. figure 3 illustrates the algorithm for the program oper- ation. see the erase/program operations table in ac
am29lv001b 14 preliminary characteristics for parameters, and to figure 15 for timing diagrams. note: see table 5 for program command sequence. figure 3. program operation chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algo- rithm automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any con- trols or timings during these operations. table 5 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the embed- ded erase algorithm are ignored. note that a hardware reset during the chip erase operation immediately ter- minates the operation. the chip erase command se- quence should be reinitiated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase op- eration by using dq7, dq6, or dq2. see write oper- ation status for information on these status bits. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. figure 4 illustrates the algorithm for the erase opera- tion. see the erase/program operations tables in ac characteristics for parameters, and to figure 16 for timing diagrams. sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two un- lock cycles, followed by a set-up command. two addi- tional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. table 5 shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram the memory prior to erase. the embedded erase algo- rithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. after the command sequence is written, a sector erase time-out of 50 s begins. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. the time be- tween these additional cycles must be less than 50 s, otherwise the last address and command might not be accepted, and erasure may begin. it is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. if the time between additional sector erase commands can be assumed to be less than 50 s, the system need not monitor dq3. any command other than sector erase or erase suspend during the time-out period resets the device to reading array data. the system must rewrite the command sequence and any additional sector addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out. (see the dq3: sector erase timer section.) the time-out begins from the rising edge of the final we# pulse in the command sequence. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. note that a hardware reset during the start write program command sequence data poll from system verify data? no yes last address? no yes programming completed increment address embedded program algorithm in progress 21557c-6
15 am29lv001b preliminary sector erase operation immediately terminates the op- eration. the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the sta- tus of the erase operation by using dq7, dq6, or dq2. (refer to write operation status for information on these status bits.) figure 4 illustrates the algorithm for the erase opera- tion. refer to the erase/program operations tables in the ac characteristics section for parameters, and to figure 16 for timing diagrams. erase suspend/erase resume commands the erase suspend command allows the system to in- terrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, including the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algo- rithm. writing the erase suspend command during the sector erase time-out immediately terminates the time-out period and suspends the erase operation. ad- dresses are dont-cares when writing the erase sus- pend command. when the erase suspend command is written during a sector erase operation, the device requires a maxi- mum of 20 s to suspend the erase operation. how- ever, when the erase suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (the device erase suspends all sectors selected for erasure.) normal read and write timings and command definitions apply. reading at any address within erase-suspended sec- tors produces status data on dq7Cdq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. see write operation status for information on these status bits. after an erase-suspended program operation is com- plete, the system can once again read array data within non-suspended sectors. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program oper- ation. see write operation status for more informa- tion. the system may also write the autoselect command sequence when the device is in the erase suspend mode. the device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. when the device exits the autoselect mode, the device reverts to the erase suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. the system must write the erase resume command (address bits are dont care) to exit the erase suspend mode and continue the sector erase operation. further writes of the resume command are ignored. another erase suspend command can be written after the de- vice has resumed erasing. notes: 1. see table 5 for erase command sequence. 2. see dq3: sector erase timer for more information. figure 4. erase operation start write erase command sequence data poll from system data = ffh? no yes erasure completed embedded erase algorithm in progress 21557c-7
am29lv001b 16 preliminary table 5. am29lv001b command definitions legend: x = dont care ra = address of the memory location to be read. rd = data read from location ra during read operation. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we# or ce# pulse. pd = data to be programmed at location pa. data is latched on the rising edge of we# or ce# pulse. sa = address of the sector to be erased or verified. address bits a16Ca12 uniquely select any sector. notes: 1. see table 1 for descriptions of bus operations. 2. all values are in hexadecimal. 3. except when reading array or autoselect data, all bus cycles are write operations. 4. address bits a16Ca11 are dont care for unlock and command cycles, unless sa or pa required. 5. no unlock or command cycles required when device is in read mode. 6. the reset command is required to return to the read mode when the device is in the autoselect mode or if dq5 goes high. 7. the fourth cycle of the autoselect command sequence is a read cycle. 8. the data is 00h for an unprotected sector and 01h for a protected sector. the complete bus address in the fourth cycle is composed of the sector address (a16Ca12), a1 = 1, and a0 = 0. 9. the unlock bypass command is required prior to the unlock bypass program command. 10. the unlock bypass reset command is required to return to reading array data when the device is in the unlock bypass mode. 11. the system may read and program functions in non- erasing sectors, or enter the autoselect mode, when in the erase suspend mode. the erase suspend command is valid only during a sector erase operation. 12. the erase resume command is valid only during the erase suspend mode. command sequence (note 1) bus cycles (notes 2C4) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 manufacturer id 4 555 aa 2aa 55 555 90 x00 01 device id, top boot block 4 555 aa 2aa 55 555 90 x01 ed device id, bottom boot block 6d sector protect verify (note 8) 4 555 aa 2aa 55 555 90 sa x02 00 01 byte program 4 555 aa 2aa 55 555 a0 pa pd unlock bypass 3 555 aa 2aa 55 555 20 unlock bypass program (note 9) 2 xxx a0 pa pd unlock bypass reset (note 10) 2 xxx 90 xxx 00 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 erase suspend (note 11) 1 xxx b0 erase resume (note 12) 1 xxx 30 cycles autoselect (note 7)
17 am29lv001b preliminary write operation status the device provides several bits to determine the sta- tus of a write operation: dq2, dq3, dq5, dq6, and dq7. table 6 and the following subsections describe the functions of these bits. dq7, and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. these three bits are discussed first. dq7: data# polling the data# polling bit, dq7, indicates to the host sys- tem whether an embedded algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the program or erase command se- quence. during the embedded program algorithm, the device outputs on dq7 the complement of the datum pro- grammed to dq7. this dq7 status also applies to pro- gramming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a program address falls within a protected sector, data# polling on dq7 is active for ap- proximately 1 s, then the device returns to reading array data. during the embedded erase algorithm, data# polling produces a 0 on dq7. when the embedded erase al- gorithm is complete, or if the device enters the erase suspend mode, data# polling produces a 1 on dq7. this is analogous to the complement/true datum output described for the embedded program algorithm: the erase function changes all the bits in a sector to 1; prior to this, the device outputs the complement, or 0. the system must provide an address within any of the sectors selected for erasure to read valid status in- formation on dq7. after an erase command sequence is written, if all sec- tors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the de- vice returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. when the system detects dq7 has changed from the complement to true data, it can read valid data at dq7C dq0 on the following read cycles. this is because dq7 may change asynchronously with dq0Cdq6 while output enable (oe#) is asserted low. figure 17, data# polling timings (during embedded algorithms), in the ac characteristics section illustrates this. table 6 shows the outputs for data# polling on dq7. figure 5 shows the data# polling algorithm. dq7 = data? yes no no dq5 = 1? no yes yes fail pass read dq7Cdq0 addr = va read dq7Cdq0 addr = va dq7 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is an address within any sector selected for erasure. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = 1 because dq7 may change simultaneously with dq5. 21557c-8 figure 5. data# polling algorithm
am29lv001b 18 preliminary dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase op- eration), and during the sector erase time-out. during an embedded program or erase algorithm op- eration, successive read cycles to any address cause dq6 to toggle (the system may use either oe# or ce# to control the read cycles). when the operation is com- plete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 tog- gles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algorithm erases the unpro- tected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to deter- mine whether a sector is actively erasing or is erase- suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device enters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alternatively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded pro- gram algorithm is complete. table 6 shows the outputs for toggle bit i on dq6. fig- ure 6 shows the toggle bit algorithm in flowchart form, and the section reading toggle bits dq6/dq2 ex- plains the algorithm. figure 18 in the ac characteris- tics section shows the toggle bit timing diagrams. figure 19 shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii. dq2: toggle bit ii the toggle bit ii on dq2, when used with dq6, indi- cates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by com- parison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to table 6 to compare outputs for dq2 and dq6. figure 6 shows the toggle bit algorithm in flowchart form, and the section reading toggle bits dq6/dq2 explains the algorithm. see also the dq6: toggle bit i subsection. figure 18 shows the toggle bit timing dia- gram. figure 19 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 6 for the following discussion. when- ever the system initially begins reading toggle bit sta- tus, it must read dq7Cdq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the tog- gle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq7Cdq0 on the fol- lowing read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially de- termines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, de- termining the status as described in the previous para- graph. alternatively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation (top of figure 6). table 6 shows the outputs for toggle bit i on dq6. fig- ure 6 shows the toggle bit algorithm. figure 18 in the ac characteristics section shows the toggle bit timing diagrams. figure 19 shows the differences between dq2 and dq6 in graphical form. see also the subsec- tion on dq2: toggle bit ii.
19 am29lv001b preliminary dq5: exceeded timing limits dq5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. under these conditions dq5 produces a 1. this is a failure condition that indicates the program or erase cycle was not successfully completed. the dq5 failure condition may appear if the system tries to program a 1 to a location that is previously pro- grammed to 0. only an erase operation can change a 0 back to a 1. under this condition, the device halts the operation, and when the operation has ex- ceeded the timing limits, dq5 produces a 1. under both these conditions, the system must issue the reset command to return the device to reading array data. dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to determine whether or not an erase operation has begun. (the sector erase timer does not apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out is complete, dq3 switches from 0 to 1. if the time between additional sector erase com- mands from the system can be assumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command sequence is written, the system should read the status on dq7 (data# poll- ing) or dq6 (toggle bit i) to ensure the device has ac- cepted the command sequence, and then read dq3. if dq3 is 1, the internally controlled erase cycle has be- gun; all further commands (other than erase suspend) are ignored until the erase operation is complete. if dq3 is 0, the device will accept additional sector erase commands. to ensure the command has been accepted, the system software should check the status of dq3 prior to and following each subsequent sector erase command. if dq3 is high on the second status check, the last command might not have been ac- cepted. table 6 shows the outputs for dq3. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7Cdq0 toggle bit = toggle? read dq7Cdq0 twice read dq7Cdq0 notes: 1. read toggle bit twice to determine whether or not it is toggling. see text. 2. recheck toggle bit because it may stop toggling as dq5 changes to 1. see text. 21557c-9 figure 6. toggle bit algorithm (note 1) (notes 1, 2)
am29lv001b 20 preliminary table 6. write operation status notes: 1. dq5 switches to 1 when an embedded program or embedded erase operation has exceeded the maximum timing limits. see dq5: exceeded timing limits for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. operation dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) standard mode embedded program algorithm dq7# toggle 0 n/a no toggle embedded erase algorithm 0 toggle 0 1 toggle erase suspend mode reading within erase suspended sector 1 no toggle 0 n/a toggle reading within non-erase suspended sector data data data data data erase-suspend-program dq7# toggle 0 n/a n/a
21 am29lv001b preliminary absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . C65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . C65 c to +125 c voltage with respect to ground all pins except a9, oe# and reset# (note 1) . . . . . . . . . . . . . . . . . . . C0.5 v to v cc +0.5 v v cc (note 1). . . . . . . . . . . . . . . . . . . . C0.5 v to +3.6 v a9 , oe# , and reset# (note 2) . . .C0.5 v to +12.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is C0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to C2.0 v for periods of up to 20 ns. see figure 7. maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods up to 20 ns. see figure 8. 2. minimum dc input voltage on pins a9, oe#, and reset# is C0.5 v. during voltage transitions, a9, oe#, and reset# may undershoot v ss to C2.0 v for periods of up to 20 ns. see figure 7. maximum dc input voltage on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the de- vice at these or any other conditions above those indi- cated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rat- ing conditions for extended periods may affect device re- liability. figure 7. maximum negative overshoot waveform figure 8. maximum positive overshoot waveform operating ranges commercial (c) devices ambient temperature (t a ) . . . . . . . . . . . 0c to +70c industrial (i) devices ambient temperature (t a ) . . . . . . . . . C40c to +85c extended (e) devices ambient temperature (t a ) . . . . . . . . C55c to +125c v cc supply voltages v cc for regulated voltage range. . . . . .+3.0 v to 3.6 v v cc for full voltage range . . . . . . . . . . .+2.7 v to 3.6 v operating ranges define those limits between which the func- tionality of the device is guaranteed. 20 ns 20 ns +0.8 v C0.5 v 20 ns C2.0 v 21557c-10 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v 21557c-1
am29lv001b 22 preliminary dc characteristics cmos compatible notes: 1. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 2. i cc active while embedded erase or embedded program is in progress. 3. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. typical sleep mode current is 200 na. 4. not 100% tested. parameter description test conditions min typ max unit i li input load current v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9 input load current v cc = v cc max ; a9 = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc active read current (note 1) ce# = v il, oe# = v ih 5 mhz 7 12 ma 1 mhz 2 4 i cc2 v cc active write current (notes 2 and 4) ce# = v il, oe# = v ih 15 30 ma i cc3 v cc standby current v cc = v cc max ; ce#, reset# = v cc 0.3 v 0.2 5 a i cc4 v cc reset current v cc = v cc max ; reset# = v ss 0.3 v 0.2 5 a i cc5 automatic sleep mode (note 3) v ih = v cc 0.3 v; v il = v ss 0.3 v 0.2 5 a v il input low voltage C0.5 0.8 v v ih input high voltage 0.7 x v cc v cc + 0.3 v v id voltage for autoselect and temporary sector unprotect v cc = 3.3 v 11.5 12.5 v v ol output low voltage i ol = 4.0 ma, v cc = v cc min 0.45 v v oh1 output high voltage i oh = C2.0 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = C100 a, v cc = v cc min v cc C0.4 v lko low v cc lock-out voltage (note 4) 2.3 2.5 v
23 am29lv001b preliminary dc characteristics (continued) zero power flash 20 15 10 5 0 0 500 1000 1500 2000 2500 3000 3500 4000 supply current in ma time in ns note: addresses are switching at 1 mhz 21557c-12 figure 9. i cc1 current vs. time (showing active and automatic sleep currents) 10 8 2 0 12345 frequency in mhz supply current in ma note: t = 25 c 21557c-13 figure 10. typical i cc1 vs. frequency 2.7 v 3.6 v 4 6
am29lv001b 24 preliminary test conditions table 7. test specifications key to switching waveforms 2.7 k w c l 6.2 k w 3.3 v device under te s t 21557c-14 figure 11. test setup note: diodes are in3064 or equivalent test condition -45r, -55 -70, -90 unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 100 pf input rise and fall times 5 ns input pulse levels 0.0C3.0 v input timing measurement reference levels 1.5 v output timing measurement reference levels 1.5 v waveform inputs outputs steady changing from h to l changing from l to h dont care, any change permitted changing, state unknown does not apply center line is high impedance state (high z) 21557c-15 3.0 v 0.0 v 1.5 v 1.5 v output measurement level input 21557c-16 figure 12. input waveforms and measurement levels
25 am29lv001b preliminary ac characteristics read operations notes: 1. not 100% tested. 2. see figure 11 and table 7 for test specifications. parameter description speed option jedec std. test setup -45r -55 -70 -90 unit t avav t rc read cycle time (note 1) min 45 55 70 90 ns t avqv t acc address to output delay ce# = v il oe# = v il max45557090ns t elqv t ce chip enable to output delay oe# = v il max45557090ns t glqv t oe output enable to output delay max 25 30 30 35 ns t ehqz t df chip enable to output high z (note 1) max 10 15 25 30 ns t ghqz t df output enable to output high z (note 1) max 10 15 25 30 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first (note 1) min 0 ns t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t oe reset# n/a am29f002nb t df t oh 21557c-17 figure 13. read operations timings
am29lv001b 26 preliminary ac characteristics hardware reset (reset#) note: not 100% tested. parameter description all speed options jedec std. test setup unit t ready reset# pin low (during embedded algorithms) to read or write (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read or write (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset# high time before read (see note) min 50 ns t rpd reset# low to standby mode min 20 s reset# n/a am29f002nb t rp t ready reset timings not during embedded algorithms ce#, oe# t rh reset timings during embedded algorithms reset# n/a am29f002nb t rp 21557c-18 figure 14. reset# timings
27 am29lv001b preliminary ac characteristics erase/program operations notes: 1. not 100% tested. 2. see the erase and programming performance section for more information. parameter -45r -55 -70 -90 jedec std. description unit t avav t wc write cycle time (note 1) min 45 55 70 90 ns t avwl t as address setup time min 0 ns t wlax t ah address hold time min 35 45 45 45 ns t dvwh t ds data setup time min 20 20 35 45 ns t whdx t dh data hold time min 0 ns t oes output enable setup time (note 1) min 0 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 25 30 35 35 ns t whwl t wph write pulse width high min 30 ns t whwh1 t whwh1 programming operation (note 2) typ 9 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.7 sec t vcs v cc setup time (note 1) min 50 s
am29lv001b 28 preliminary ac characteristics oe# we# ce# v cc data addresses t ds t ah t dh t wp pd t whwh1 t wc t as t wph t vcs 555h pa pa read status data (last two cycles) a0h t ghwl t cs status d out program command sequence (last two cycles) t ch pa notes: 1. pa = program address, pd = program data, d out is the true data at the program address. 21557c-19 figure 15. program operation timings
29 am29lv001b preliminary ac characteristics oe# ce# addresses v cc we# data 2aah sa t ghwl t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 30h t ds t vcs t cs t dh 55h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data note: sa = sector address (for sector erase), va = valid address for reading status data (see write operation status). 21557c-20 figure 16. chip/sector erase operation timings
am29lv001b 30 preliminary ac characteristics we# ce# oe# high z t oe high z dq7 dq0Cdq6 complement true addresses va t oeh t ce t ch t oh t df va va status data complement status data true valid data valid data t acc t rc note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read c ycle. 21557c-21 figure 17. data# polling timings (during embedded algorithms) we# ce# oe# high z t oe dq6/dq2 addresses va t oeh t ce t ch t oh t df va va t acc t rc valid data valid status valid status (first read) (second read) (stops toggling) valid status va note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cy cle, and array data read cycle. 21557c-22 figure 18. toggle bit timings (during embedded algorithms)
31 am29lv001b preliminary ac characteristics temporary sector unprotect note: not 100% tested. parameter all speed options jedec std. description unit t vidr v id rise and fall time min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s note: the system can use oe# or ce# to toggle dq2/dq6. dq2 toggles only when read at an address within an erase-suspended sector. 21557c-23 figure 19. dq2 vs. dq6 enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing reset# t vidr 12 v 0 or 3 v ce# we# ry/by# t vidr t rsp program or erase command sequence 0 or 3 v 21557c-24 figure 20. temporary sector unprotect timing diagram
am29lv001b 32 preliminary ac characteristics sector protect: 100 s sector unprot ect: 10 ms 1 s r eset# sa, a6, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector protect/unprotect verify v id v ih note: for sector protect, a6 = 0, a1 = 1, a0 = 0. for sector unprotect, a6 = 1, a1 = 1, a0 = 0. 21557c-25 figure 21. in-system sector protect/unprotect timing diagram
33 am29lv001b preliminary ac characteristics alternate ce# controlled erase/program operations notes: 1. not 100% tested. 2. see the erase and programming performance section for more information. parameter -45 -55 -70 -90 jedec std. description unit t avav t wc write cycle time (note 1) min 45 55 70 90 ns t avel t as address setup time min 0 ns t elax t ah address hold time min 35 45 45 45 ns t dveh t ds data setup time min 20 20 35 45 ns t ehdx t dh data hold time min 0 ns t oes output enable setup time (note 1) min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 25 30 35 35 ns t ehel t cph ce# pulse width high min 30 ns t whwh1 t whwh1 programming operation (notes 1, 2) typ 9 s t whwh2 t whwh2 sector erase operation (notes 1, 2) typ 0.7 sec
am29lv001b 34 preliminary ac characteristics t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling a0 for program 55 for erase t rh t whwh1 or 2 t wh pd for program 30 for sector erase 10 for chip erase 555 for program 2aa for erase pa for program sa for sector erase 555 for chip erase notes: 1. figure indicates the last two bus cycles of the program or erase command sequence. 2. pa program address, sa = sector address, pd = program data, dq7# = complement of the data written to the device, d out = data written to the device. 21557c-26 figure 22. alternate ce# controlled write operation timings
35 am29lv001b preliminary erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c, 3.0 v v cc , 1,000,000 cycles. additionally, programming typicals assume checkerboard pattern. 2. under worst case conditions of 90c, v cc = 2.7 v (3.0 v for -45r), 1,000,000 cycles. 3. the typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. in the pre-programming step of the embedded erase algorithm, all bytes are programmed to 00h before erasure. 5. system-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. see table 5 for further information on command definitions. 6. the device has a minimum erase and program cycle endurance of 1,000,000 cycles. latchup characteristics includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. tsop pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. plcc pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter typ (note 1) max (note 2) unit comments sector erase time 0.7 15 s excludes 00h programming prior to erasure (note 4) chip erase time 7 s byte programming time 9 300 s excludes system level overhead (note 5) chip programming time (note 3) 1.1 3.3 s description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) C1.0 v 13.0 v input voltage with respect to v ss on all i/o pins C1.0 v v cc + 1.0 v v cc current C100 ma +100 ma parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 6 7.5 pf c out output capacitance v out = 0 8.5 12 pf c in2 control pin capacitance v in = 0 7.5 9 pf parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 4 6 pf c out output capacitance v out = 0 8 12 pf c in2 control pin capacitance v pp = 0 8 12 pf
am29lv001b 36 preliminary physical dimensions pl 032 32-pin plastic leaded chip carrier (measured in inches) .050 ref. .026 .032 top view pin 1 i.d. .485 .495 .447 .453 .585 .595 .547 .553 16-038fpo-5 pl 032 da79 6-28-94 ae side view seating plane .125 .140 .009 .015 .080 .095 .042 .056 .013 .021 .400 ref. .490 .530
37 am29lv001b preliminary physical dimensions* ts 032 32-pin standard thin small outline package (measured in millimeters) * for reference only. bsc is an ansi standard for basic space centering pin 1 i.d. 1 18.30 18.50 7.90 8.10 0.50 bsc 0.05 0.15 0.95 1.05 16-038-tsop-2 ts 032 da95 3-25-97 lv 19.80 20.20 1.20 max 0.50 0.70 0.10 0.21 0? 5? 0.08 0.20
am29lv001b 38 preliminary physical dimensions* tsr032 32-pin reverse thin small outline package (measured in millimeters) * for reference only. bsc is an ansi standard for basic space centering revision summary for am29lv001b revision b split the am29lv001b/am29lv010b data sheet, with the elimination of all references to am29lv010b. revision c global deleted 120 ns speed option; added 90 ns speed option. distinctive characteristics changed process technology to 0.33 m. temporary sector unprotect entered timing specifications for t vidr and t rsp . erase and programming performance changed endurance in note 2 to 1 million cycles; added worst case voltage for -45r speed option. trademarks copyright ? 1998 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies . 1 18.30 18.50 19.80 20.20 7.90 8.10 0.50 bsc 0.05 0.15 0.95 1.05 16-038-tsop-2 tsr032 da95 4-4-95 ae pin 1 i.d. 1.20 max 0.50 0.70 0.10 0.21 0.25mm (0.0098") bsc 0 5 0.08 0.20

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